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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9850/D Rev 0, 03/2003
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Clock Generator for PowerQUICC III
The MPC9850 is a PLL based clock generator specifically designed for Motorola Microprocessor And Microcontroller applications including the PowerQUICC III. This device generates a microprocessor input clock plus the 500 MHz Rapid I/O clock. The microprocessor clock is selectable in output frequency to any of the commonly used microprocessor input and bus frequencies. The Rapid I/O outputs are LVDS compatible. The device offers eight low skew clock outputs organized into two output banks, each configurable to support different clock frequencies. The extended temperature range of the MPC9850 supports telecommunication and networking requirements.
MPC9850
MICROPROCESSOR CLOCK GENERATOR
* * * * * * * * * * * *
Features 8 LVCMOS outputs for processor and other circuitry 2 differential LVDS outputs for Rapid I/O interface Crystal oscillator or external reference input 25 or 33 MHz Input reference frequency Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66, 50, 33 or 16 MHz Buffered reference clock output Rapid I/O (LVDS) Output = 500, 250 or 125 MHz Low cycle-to-cycle and period jitter 100 lead PBGA package 3.3V supply with 3.3V or 2.5V (Bank B) output LVCMOS drive Supports computing, networking, telecommunications applications
VF SUFFIX 100-LEAD MAP BGA PACKAGE CASE 1462
Ambient temperature range -40C to +85C Functional Description The MPC9850 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers, divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60 or 120 to produce output frequencies of 200, 166, 133, 125, 111, 100, 83 66 50 33 or 16 MHz. The single-ended LVCMOS outputs are divided into two banks of 4 low skew outputs each, for use in driving a microprocessor or microcontroller clock input as well as other system components. The 2 GHz PLL output frequency is also divided to produce a 125, 250 or 500 MHz clock output for Rapid I/O applications such as found on the PowerQUICC III communications processor. The input reference, either crystal or external input is also buffered to a separate output that my be used as the clock source for a Gigabit Ethernet PHY if desired. The reference clock may be provided by either an external clock input of 25 MHz or 33 MHz. An internal oscillator requiring a 25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal oscillator or external clock input is selected via the input pin of REF_SEL. Other than the crystal, no external components are required for crystal oscillator operation. The REF_33MHz configuration pins is used to select between a 33 and 25 MHz input frequency. The MPC9850 is packaged in a 100 lead MAPBGA package to optimize both performance and board density.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
(c) Motorola, Inc. 2003
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MPC9850
CLK PCLK1 PCLK1 REF_CLK_SEL XTAL_IN
0 1 0 1
BN
QA0 QA1
Ref
1
0
PLL 2000 MHz OSC
QA2 QA3
XTAL_OUT REF_SEL
BN
QB0 QB1 QB2 QB3
PLL_BYPASS REF_33MHz
CLK_A[0:5] CLK_B[0:5] RIO_C[0:1] MR
B4, 8, 16
QC0 QC0 QC1 QC1 REF_OUT
Figure 1. MPC9850 Block Diagram Table 1. PIN CONFIGURATIONS
Pin CLK PCLK, PCLK QA0, QA1, QA2, QA3 QB0, QB1, QB2, QB3 QC0, QC1, QC0, QC1 REF_OUT XTAL_IN XTAL_OUT REF_CLK_SEL REF_SEL REF_33MHz MR PLL_BYPASS CLK_A[0:5]a CLK_B[0:5]b RIO_C [0:1] VDD VDDA VDDOB GND a. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) b. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) c. PowerPC bit ordering (bit 0 = msb, bit 1 = lsb) I/O Input Input Output Output Output Output Input Output Input Input Input Input Input Input Input Input Type LVCMOS LVPECL LVCMOS LVCMOS LVDS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Function PLL reference clock input (pull-down) PLL reference clock input (PCLK - pull-down, PCLK - pull-up and pull-down) Bank A Outputs Bank B Outputs Bank C Outputs Reference Output (25 MHz or 33 MHz) Crystal Oscillator Input Pin Crystal Oscillator Output Pin Select between CLK and PCLK input (pull-down) Select between External Input and Crystal Oscillator Input (pull-down) Selects 33MHz input (pull-down) Master Reset (pull-up) Select PLL or static test mode (pull-down) Configures Bank A clock output frequency (pull-up) Configures Bank B clock output frequency (pull-up) Configures Bank C clock output frequency (pull-down) 3.3 V Supply Analog Supply Supply for Output Bank B Ground VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDOB VDD high high high low high high high Supply VDD VDD VDDOA VDD Active/State
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Table 2. FUNCTION TABLE
Control REF_CLK_SEL REF_SEL PLL_BYPASS REF_33MHz MR Default 0 0 0 0 1 0 CLK0 CLKx Normal Selects 25MHz Reference Reset 1 CLK1 XTAL Bypass Selects 33MHz Reference Normal
CLK_A, CLK_B, and RIO_C control output frequencies. See Table 3 and Table 4 for specific device configuration
Table 3. OUTPUT CONFIGURATIONS (BANKS A & B)
CLK_x[0:5]a 111111 111100 101000 011110 010100 001111 001100 001010 001001 001000 000111 000110 000101 000100 CLK_x[0] (msb) 1 1 1 0 0 0 0 0 0 0 0 0 0 0 CLK_x[1] 1 1 0 1 1 0 0 0 0 0 0 0 0 0 CLK_x[2] 1 1 1 1 0 1 1 1 1 1 0 0 0 0 CLK_x[3] 1 1 0 1 1 1 1 0 0 0 1 1 1 1 CLK_x[4] 1 0 0 1 0 1 0 1 0 0 1 1 0 0 CLK_x[5] (lsb) 1 0 0 0 0 1 0 0 1 0 1 0 1 0 N 128 120 80 60 40 30 24 20 18 16 15 12 10 8b Frequency (MHz) 15.87 16.67 25.00 33.33 50.00 66.67 83.33 100.00 111.11 125.00 133.33 166.67 200.00 250
a. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) b. Minimum value for N
Table 4. OUTPUT CONFIGURATIONS (BANK C)
RIO_C[0:1] 00 01 10 11 Frequency (MHz) 50 (test output) 125 250 500
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OPERATION INFORMATION
Output Frequency Configuration The MPC9850 was designed to provide the commonly used frequencies in PowerQUICC, PowerPC and other microprocessor systems. Table 3 lists the configuration values that will generate those common frequencies. The MPC9850 can generate numerous other frequencies that may be useful in specific applications. The output frequency (fout) of either Bank A or Bank B may be calculated by the following equation. fout = 2000 / N where fout is in MHz and N = 2 * CLK_x[0:5] This calculation is valid for all values of N from 8 to 126. Note that N = 15 is a modified case of the configuration inputs CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to 00111 or 7. Crystal Input Operation TBD Power-Up and MR Operation Figure 2 defines the release time and the minumum pulse length for MR pin. The MR release time is based upon the power supply being stable and within VDD specifications. See Table 11 for actual parameter values. The MPC9850 may be configured after release of reset and the outputs will be stable for use after lock indication is obtained.
VDD
MR treset_rel treset_pulse
Figure 2. MR operation Power Supply Bypassing VDD VDD The MPC9850 is a mixed analog/digital product. The architecture of the MPC9850 supports low noise signal TBD TBD MPC9850 operation at high frequencies. In order to maintain its superior RS signal quality, all V DD pins should be bypassed by VDDA high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching TBD noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low Figure 3. VCC Power Supply Bypass impedance path to ground exists for frequencies well above the noise bandwidth.
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Table 5. ABSOLUTE MAXIMUM RATINGSa
Symbol VDD VDDC VDDOB VIN VOUT IIN IOUT TS Characteristics Supply Voltage (core) Supply Voltage (Analog Supply Voltage) Supply Voltage (LVCMOS output for Bank B) DC Input Voltage DC Output Voltageb DC Input Current DC Output Current Storage Temperature -65 Min -0.3 -0.3 -0.3 -0.3 -0.3 Max 3.8 VDD VDD VDD+0.3 VDDx+0.3 20 50 125 Unit V V V V V mA mA C Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. b. VDDx references power supply pin associated with specific output pin.
Table 6. GENERAL SPECIFICATIONS
Symbol VTT MM HBM CDM LU CIN JC Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model Latch-Up Immunity Input capacitance Thermal resistance (junction-to-ambient, junction-toboard, junction-to-case) TBD TBD TBD 200 TBD TBD Min Typ VDD / 2 Max Unit V V V V mA pF C/W Inputs Condition
TA Ambient Temperaturea -40 85 C a. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MPC9850 to be used in applications requiring industrial temperature range. It is recommended that users of the MPC9850 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application.
Table 7. DC CHARACTERISTICS (TA = -40C to 85C)
Symbol Characteristics Min Typ Max Unit Condition Supply Current for VDD=3.3V5% and VDDOB = 3.3V5% IDD IDDC IDDOB IDD IDDC IDDOB Maximum Quiescent Supply Current (Core) Maximum Quiescent Supply Current (Analog Supply) Maximum Bank B Supply Current TBD TBD TBD TBD TBD TBD mA mA mA VDD pins VDDIN pins VDDOB pins VDD pins VDDIN pins VDDOB pins
Supply Current for VDD=3.3V5% and VDDOB = 2.5V5% Maximum Quiescent Supply Current (Core) Maximum Quiescent Supply Current (Analog Supply) Maximum Bank B Supply Current TBD TBD TBD TBD TBD TBD mA mA mA
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Table 8. LVDS DC CHARACTERISTICS (TA = -40C to 85C)
Symbol Characteristics Min Typ Max Unit Condition Differential LVDS clock outputs (QC0, QC0 Cnd QC1, QC1) for VDD=3.3V5% VPP Output Differential Voltagea (peak-to-peak) (LVDS) 250 mV VOS Output Offset Voltage (LVDS) 1125 1275 mV a. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
Table 9. LVPECL DC CHARACTERISTICS (TA = -40C to 85C)a
Symbol Characteristics Min Typ Max Unit Condition Differential LVPECL clock inputs (CLK1, CLK1 ) for VDD=3.3V0.5% VPP Differential Voltageb (peak-to-peak) (LVPECL) 250 mV VCMR 1.0 VDD - 0.6 V a. AC characteristics are design targets and pending characterization. b. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. c. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. Differential Input Crosspoint Voltagec (LVPECL)
Table 10. LVCMOS I/O DC CHARACTERISTICS (TA = -40C to 85C)
Symbol LVCMOS for VDD=3.3V5% VIH VIL IIN VOH VOL ZOUT VOH VOL Input High Voltage Input Low Voltage Input Currenta 2.0 VDD + 0.3 0.8 10 V V C LVCMOS LVCMOS VIN=VDDL or GND IOH=-24 ma IOL= 24 ma Characteristics Min Typ Max Unit Condition
LVCMOS for VDD=3.3V5% and VDDOB = 3.3V5% Output High Voltage Output Low Voltage Output Impedance 14 2.4 0.4 V V
W
V 0.4 V
LVCMOS for VDD=3.3V5% and VDDOB = 2.5V5% Output High Voltage Output Low Voltage 22 1.9 IOH=-15 ma IOL= 15 ma
ZOUT Output Impedance a. Inputs have pull-down resistors affecting the input current.
W
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Table 11. AC CHARACTERISTICS (VDD=3.3V5%, VDDOB=3.3V5%, TA= -40C to +85C)a b
Symbol Characteristics Min Typ Max Unit Condition Input and output timing specification fref Input reference frequency (25 MHz input) Input reference frequency (33 MHz input) XTAL Input Input reference frequency in PLL bypass modec VCO frequency ranged Output Frequency Bank C output Bank B output Bank C output TBD 100 TBD 47.5 50 TBD 52.5 TBD TBD TBD 25 33 25 2000 TBD TBD TBD TBD TBD TBD TBD MHz MHz MHz PLL bypass MHz MHz MHz MHz ps ppm ns % 20% to 80% PLL locked
fVCO fMCX
frefPW frefCcc tr, tf DC
Reference Input Pulse Width Input Frequency Accuracy Output Rise/Fall Time Output duty cycle PLL closed loop bandwidthe Maximum PLL Lock Time MR hold time on power up MR hold time
PLL specifications BW tLOCK treset_ref treset_pulse TBD 10 TBD TBD kHz ms ns ns
Skew and jitter specifications tsk(O) tsk(O) tJIT(CC) tJIT(PER) tJIT() a. b. c. d. e. f. Output-to-output Skew (within a bank) Output-to-output Skew (across banks A and B) Cycle-to-cycle jitter Period Jitter I/O Phase Jitter RMS (1 )f RMS (1 ) RMS (1 ) TBD TBD 50 100 10 ps ps ps ps ps VDDOB = 3.3V
tr, tf Output Rise/Fall Time TBD ns 20% to 80% AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. In bypass mode, the MPC9850 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = (fVCO / M) N. -3 dB point of PLL transfer characteristics. See application note AN1934 for a jitter calculation for other confidence factors than 1
s.
ZO = 50 Pulse Generator Z = 50W ZO = 50 RT = 100 RT = 50 VTT DUT MPC9850
Figure 4. MPC9850 AC test reference (LVDS outputs)
Pulse Generator Z = 50W
ZO = 50
ZO = 50
RT = 50 VTT
DUT MPC9850
RT = 50 VTT
Figure 5. MPC9850 AC test reference (LVCMOS outputs)
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Table 12. MPC9850 Pin Diagram (Top View)
1 A B C D E F G H J K VDDOB VDDOB RSVD VDDA REF_SEL PCLK REF_CLK_SEL XTAL_IN VDDOB VDDOB 2 VDDOB VDDOB RSVD VDDA CLK PCLK REF_33MHz XTAL_OUT VDDOB VDDOB 3 CLKA[1] CLKA[0] VDD VDD VDD VDD VDD VDD CLKB[0] CLKB[1] 4 CLKA[3] CLKA[2] VDD GND GND GND GND VDD CLK[2] CLKB[3] 5 CLKA[5] CLKA[4] VDD GND GND GND GND VDD CLK[4] CLKB[5] 6 VDD QA0 VDD GND GND GND GND VDD QB0 VDDOB 7 QA1 VDD VDD GND GND GND GND VDD VDDOB QB1 8 QA2 QA3 VDD VDD VDD VDD VDD VDD QB3 QB2 9 VDDOB VDDOB VDD QC0 VDD QC1 PLL_BYPASS RIO_C[1] VDDOB VDDOB 10 VDDOB VDDOB REF_OUT QC0 GND QC1 MR RIO_C[0] VDDOB VDDOB
Table 13. MPC9850 Pin List
Signal VDDOB VDDOB CLKA[1] CLKA[3] CLKA[5] VDD QA1 QA2 VDDOB VDDOB VDDOB VDDOB CLKA[0] CLKA[2] CLKA[4] QA0 VDD QA3 VDDOB 100 Pin MAPBGA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 Signal RSVDa RSVDa VDD VDD VDD VDD VDD VDD VDD REF_OUT VDDA VDDA VDD GND GND GND GND VDD QC0 100 Pin MAPBGA C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Signal REF_SEL CLK VDD GND GND GND GND VDD VDD GND PCLK PCLK VDD GND GND GND GND VDD QC1 QC1 100 Pin MAPBGA E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 Signal REF_CLK_SEL REF_33MHz VDD GND GND GND GND VDD PLL_BYPASS MR XTAL_IN XTAL_OUT VDD VDD VDD VDD VDD VDD RIO_C[1] RIO_C[0] 100 Pin MAPBGA G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 Signal VDDOB VDDOB CLKB[0] CLKB[2] CLKB[4] QB0 VDDOB QB3 VDDOB VDDOB VDDOB VDDOB CLKB[1] CLKB[3] CLKB[5] VDDOB QB1 QB2 VDDOB VDDOB 100 Pin MAPBGA J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10
VDDOB B10 QC0 a. RSVD pins must be left open.
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OUTLINE DIMENSIONS
VF SUFFIX 100-LEAD MAP BGA PACKAGE CASE 1462-01 ISSUE O
11
A1 INDEX AREA
B C K
11
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGING
TOP VIEW
4X
0.2
SIDE VIEW
9X
1 0.5 5 0.35 A (1.18)
K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 100X 9X
1
1.7 MAX
0.43 0.29 0.5 0.55 0.45 0.25 0.10 BOTTOM VIEW 3
M M
4
A
SEATING PLANE
100X
0.12 A
ROTATED 90 _CLOCKWISE
DETAIL K
ABC A
A1 INDEX AREA
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NOTES
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NOTES
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E Motorola Inc. 2003
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